The Z50Bus is a suggestion for a system expansion bus for 8-bit microcomputers. It’s designed to be compact, yet compatible, taking inspiration from previous standard bus layouts, and bringing it into a modern age. Being also inspired by the popular RC2014, it allows for easy adaptation of existing designs. The name of the Z50Bus comes from being originally designed to use a 50-pin connector to integrate a system around a Z80 CPU. Being a simple bus specification, it is possible to use/integrate it with other 8-bit CPUs using some glue logic.
Signal levels and descriptions
Signal levels are 5V Single Ended, with HC TTL levels expected. So, each signal uses a single line, and an active high signal will have a High at 3.5V – 5V, and a Low state at 0-1V. The 5V and GND lines are the only supply voltages on the bus. System implementations should make sure these are noise-free, well decoupled, and dimensioned for the system current draw.
The bus uses a double-row connector scheme, with the following pin layout
|49||IEO (*)||IEI (*)||50|
Female bus – Male card
* Note that IEO/IEI forms an Interrupt Enable Chain, where the IEO of a higher priority card needs to connect to a lower priority card. This means a bus board needs to connect IEO of one “slot” to the IEI of the next. It also means cards need to be present “in order”, or empty slots need IEI/IEO jumpered for interrupts to work.
This layout of the signals is relatively simple to lay out for both CPU and expansion cards. Additionally, it is easily “unfolded” onto a single-row implementation, where using the first 42 pins mapped onto a 1×40 connector gives full compatibility with the bus layout of the RC2014 compatible ecosystem.
The on-bus signals function/description closely follow Z80 CPU signals, with a few extra signals inspired/compatible with the RC2014 signal set:
|D7..D0||Data bus lines|
|Clock||System / CPU Clock (Phi2Out for 6502)|
|/Rst||System Reset, Active Low|
|/Mreq||Memory Request, Active Low, CPU Output|
|/IOreq||IO Request, Active Low, CPU Output (synthetic for 6502)|
|/WR||Write, Active Low, CPU Output|
|/RD||Read, Active Low, CPU Output|
Machine Cycle One, Active Low, CPU Output (M1+IORQ active indicates INTAck. May use SYNC on 6502)
Interrupt, Active Low, CPU Input, device requests interrupt by pulling INT low.
Non Maskable Interrupt, Active Low, CPU Input, device requests interrupt by pulling INT low.
Wait, Active Low, CPU Input, used to hold the CPU for wait states (can integrate RDY for 6502)
Halted, Active Low, CPU Output, indicates that the CPU is in WAIT FOR INTERRUPT state (HALT or WAI instructions)
Bus Request, Active Low, CPU Input, used to request bus control, i.e. for DMA
Bus Acknowledge, Active Low, CPU Output, indicates that a BusRQ is accepted, and that CPU signals are high-Z
DRAM Refresh cycle, Active Low, CPU Output. When Refresh and Mreq are active, a DRAM refresh can be done
Interrupt Enable Out, Active High output from one expansion card to next expansion.
Interrupt Enable In, Active High input to expansion from previous expansion card or system/CPU board
|Tx / Rx||System internal TTL Serial|
User Definable pins (USER1…4 on RC2014, note numbering difference)
The signal layout for Z50Bus is simplistic, and makes very little attempt at being a signal balanced and noise cancelling bus design. The bus specification itself does not indicate if a system should use buffered bus or buffered expansions (or be raw CPU signals).
Mechanical implementation and suggestions
The standard bus connector to be used, is 50-pin dual-row header pin and socket, with 2.54mm pin pitch. For expansion cards that plug into a busboard, a Male pin header with nominal 6mm pin length should be used (“standard” header, sometimes called 11mm). The bus-side connector should be a Female PCB Header Socket, with nominal 8.5mm height.
The suggested arrangement for expansion cards is to use a Right angled connector. For orientation, an expansion card laid out so the connector is on the right hand side should have pins 1 and 2 as the top pair, 49 & 50 the bottom, and the connector on the component side.
Mechanical layout is not strictly bound by the bus layout and design, but to allow for card supports, the following suggestions apply. On an expansion card, the center pair of pins (and thus the center of the connector) should be located 50mm from the edge closest to the connector pins 1 & 2. Pin 26, the middle pin closest to the bus-side edge of the card, should be located 3.75mm from the card edge. The card should leave space for a support raiser going 2.5mm in from the edge closest to pins 1 & 2, extending 20mm along that edge.
Three suggested card sizes are recommended, but not required. “Standard card” is suggested as a 100x100mm card. “Half card” is not literally half, but suggested as a 75mmx100mm card, where the bus connector is on a “long” side. “Large card” is suggested to be 100x150mm, where the bus connector is located on the “long” side, respecting the rule of locating pins 25/26. Using the recommended sizes will give a coherent look and predictable mechanicals.
For connectors used to connect a system board and expansion or bus-board, the suggested arrangement is to use straight connectors placed on-edge, female connector on the system board (main bus) side, and male on the expansion (exp bus) side. This allows the main-bus card and the exp-bus card to lie in the same plane, without requiring expensive right-angle 2×25 socket headers.
Using the Z50Bus with the 6502
Being a bus for 8-bit microcomputers designed after 2016, the number of potential CPU’s relevant for new designs is limited. Currently only the Z80-family and the 65×02 family of CPU’s have parts still in production. Because of this, only a 65×02 adaption of the bus is suggested here.
Some of the Z80-style signals need to be synthesized. 65×02 uses memory mapped IO, so the IOReq signal needs to be generated by the CPU card/system when a request is made to the 65×02 IO address space selected for the system. The Mreq signal will then be a simple invert of the IOReq signal. An equivalent function of the WAIT and HALT signals may be found on the 65×02 RDY line. A diode split of the function may be appropriate. The SYNC signal can be adapted for the M1 signal function, if the INTAck feature is considered in the implementation.
|65C02S signal||Z50Bus||Z80 signal||RC2014|
|PH2 (clk out)||CLK||CLK||CLK|
|VP (Jump to GND)|
There exists a 65c02 CPU card for the RC2014 system, this should be seen as the reference implementation when adapted to Z50Bus layout for the basic signals. See http://ancientcomputing.blogspot.no/2017/05/a-6502-cpu-for-rc2014-part-1.html. It is suggested that 65×02 based systems using the Z50Bus indicate clearly that not all expansion cards designed for a Z80 native Z50Bus system will be compatible.
A 5-slot back-plane with pass-through connections is available. The back-plane is designed to accept five expansion cards, and to connect to a host system using a male Z50Bus connection on the right side. The pass-through connector is placed on the left side, allowing for daisy-chaining of multiple back-plane cards. This card is fully passive, so any buffering needs to be done on either the host system, or on the expansion cards.
This simple adapter allows connection of RC2014-compatible expansion cards on a Z50Bus, or fast prototyping of native Z50 cards by using single-row header connectors during initial prototyping stages
This is a perf-board style prototyping card, with a full Z50Bus connection conveniently brought out on easily available pads.